The invention relates to a method of interleaving. Interleaving is the process of changing the sequence of samples in a data stream.
The invention may be used, inter alia, in receivers and transmitters, in particular for Digital Audio Broadcast (DAB) or Digital Video Broadcast receiver (DVB). In a transmitter, a digital signal to be transmitted can be interleaved. Accordingly, in a corresponding receiver, a digital baseband signal should be in a manner interleaved complementary to restore the original sequence of samples. In information transmission, interleaving helps to counteract deficiencies in the channel via which the information is transmitted. For example, in mobile reception of a radio signal there is fading which may cause a burst of errors in the demodulated signal. These errors are dispersed by interleaving the demodulated signal. Dispersed errors can be corrected by means of appropriate decoding techniques.
The invention may be embodied in an interleaving arrangement comprising a memory and a memory control unit. The invention may also be embodied in a memory control unit as such, for example, in the form of an integrated circuit. The memory control unit itself may comprise a memory in which instructions are stored for carrying out a method of interleaving according to the invention.
More specifically, the invention relates to a method of interleaving a digital signal as defined in the pre-characterizing part of Claim 1. Such a method is part of a DAB standard laid down in ETSI PRETS 3041 Final Draft. According to the DAB standard, a convolutional encoded datastream is interleaved at the transmitter side. The process of restoring the original sample sequence at the receiving side is referred to as de-interleaving. It should be noted that in this specification the term interleaving is used as a generic term which also includes de-interleaving.
The DAB method of interleaving at the transmitter side is illustrated in FIG. 1 of the application. Subsequent samples of a convolutional encoded datastream DB are delayed in accordance with a cyclically repeated delay pattern. This delay pattern is represented by an array of 16 rectangles in FIG. 1 which functionally represent 16 different delays. Each delay is an integral number of times the duration of a frame into which a DAB signal can be subdivided. The duration of a frame, denoted as FR in FIG. 1, can be considered as a unit delay. This unit delay depends on the DAB system mode in accordance with which the information is transmitted. The unit delay is 24 milliseconds.
The DAB method of interleaving functionally proceeds as follows. When a certain sample occurs in the convolutional encoded datastream DB, say sample S1, the switches SWI and SWO are in a position as shown in FIG. 1. Accordingly, sample S1 is delayed zero times the unit delay, that is, sample S1 is not delayed. When a subsequent sample occurs, say sample S2, switches SWI and SWO have moved one position downwards. Accordingly, sample S2 is delayed eight times the unit delay. Switches SWI and SWO continue to move one position downwards at each new, subsequent sample which is delayed in accordance with the numeral in the relevant rectangle in FIG. 1. When the 16th sample S16 occurs the switches will connect the bottom rectangle representing a delay of 15 unit delays. Subsequent to this position, switches SWI and SWO return to the position shown in FIG. 1. Then, the above-described process is repeated, starting with the 17th sample S17. Accordingly, this sample is not delayed like sample S1, the 18th sample S18 eight times the unit delay, and so on.
The above citations are hereby incorporated in whole by reference.
An object of the invention is, to provide a method of interleaving as identified above, which can be performed with a relatively low speed memory. Such a method is defined in Claim 1. In addition, the invention provides a receiver as defined in Claim 2, a transmitter as defined in Claim 3 an interleaving arrangement as defined in Claim 4, and a memory control unit as defined in Claim 5.
Briefly, in the invention select lines of a memory are cyclically activated at a cycle rate equal to unit delay. During the activation of a select line both data is written and read from memory locations coupled to the select line. The data written comprises a relevant bit of each sample to be delayed in an integral number of sample groups. Each sample group is associated with one delay pattern cycle. The data read comprises a number of bits which is equal to the number of bits written. The bits are read in accordance with the delay pattern.
Accordingly, for most memory accesses a newly accessed memory location is coupled to an identical select line as the previously accessed memory location. Such accesses require one clock cycle. In the invention random accesses are kept to a minimum. Random accesses are accesses for which two new mutually rectangular select lines, i.e. a row and a column, have to be activated. In a DRAM memory, this requires two clock cycles or more. When only one new select line has to be activated, one clock cycle suffices.
Hence, in the invention the average number of clock cycles needed for a memory access is close to one. The lower this average number of clock cycles, the more relaxed the speed requirement on the memory. This can be explained as follows.
The sample or bit rate of the digital signal to be interleaved determines the required number of accesses in a given time-span, say, one second. The higher the average number of clock cycles for a memory access, the more clock cycles are needed in one second to effectuate the clock frequency required number of accesses. This means that the needs to be higher, because the clock frequency is equal to the number of clock cycles in one second. Hence, a lower speed memory can perform interleaving if the average number of clock cycles for an access is lowered.
It may seem illogical that the storage capacity of the memory is not fully exploited, which will be the case in most practical applications of the invention. In commercially available memories, the number of memory locations coupled to a select line, i.e. a row or a column, is usually fixed and equals a power of two, for example 512. Generally, not all of these available memory locations will be used in the invention. This is a consequence of writing bits of an integral number of sample groups (integer) on a row or a column repetitively each unit delay. The integer is the only parameter for varying the total number of bits stored on a row or column. Generally, there will be no integer with which all available memory locations are used. Either the integer is such that some available memory locations are unused, or the integer is such that the number of bits stored exceeds the storage capacity of a row or column.
In addition to interleaving with low speed memories, the invention provides other notable features. These include low power operation, avoidance of memory refresh cycles, and relatively few and simple address calculations.